The use of secondary voltage rails in an integrated circuit (“IC”) is well known to selectively control the voltage supplied to one or more IC components. For instance, an IC may include one or more first power rails (e.g., one or more main power rails) that provides power to the entire IC. The first power rail may be powered externally by either a battery or by a power supply directly connected to a power distribution service. When the device is turned on, power from the battery or the power supply connects to the IC and charges the first power rail(s). Instead of connecting all IC components to the first power rail, one or more components of the IC may be connected to a secondary voltage rail that is selectively switched on or off using a selectively controllable switch.
This ability to selectively switch components on or off in an IC is particularly important in handheld devices including, but not limited to, cell phones, personal digital assistants, portable entertainment systems, etc. In such handheld devices, reducing the net power consumption of the device lengthens the amount of time between charges (or between replacement) of a battery power source. However, it is recognized that the selective ability to switch components on or off in an IC is also important to traditional computer systems that are not dependent upon a battery source. For instance, laptops are often designed to dissipate the least amount of heat so that the user is comfortable placing the system on her lap. It may further be valuable to reduce the net power consumed on a traditional computer system, thereby limiting the amount of fossil fuels consumed to generate the necessary electricity to power traditional computer systems. It is further recognized that the physical size of ICs and/or computer systems and the amount of operating noise associated with an IC and/or computer system may also decrease as the number and size of heat sinks and fans is reduced.
Conventionally, one or more switches in an IC are used to selectively switch a voltage rail on or off, thereby selectively powering up or down components connected to the voltage rail. In this manner, the multiple voltage rails may serve to create voltage domains by dividing an IC into voltage islands. In some prior art ICs, more than one voltage rail may be provided, thereby creating multiple voltage islands, each operating at the same or different voltage levels. It is also recognized that one or more voltage rails may operate at a different voltage level than the first power rail. However, the mechanism(s) used to transform the voltage from the level provided on the first power rail (e.g., Vdd, global) to the level provided on a given voltage rail (e.g., Vdd, int), being well known, will not be discussed or illustrated so as not to obscure the present disclosure. Instead, each of the voltage rails discussed and illustrated in the present document are operational to provide the same voltage level (or, due to non-ideal components, nearly the same voltage level) as the first power rail. It will further be appreciated by those of ordinary skill in the art that the added clarity provided by describing the invention with reference to a first (e.g., main) power rail and secondary voltage rails having the same (or similar) voltages is not meant to limit or constrain the invention to only two such rails or to rails with the same (or similar) voltages.
In conventional circuits, transistors may be used to implement the one or more switches that power up a given secondary voltage rail. For instance, FIG. 1 illustrates a prior art example of a circuit 100 having a first power rail 102, a secondary voltage rail 104, and a plurality of switches 105. As illustrated, the plurality of switches 105 includes a plurality of PMOS transistors 106-110 and a plurality of buffers 116-120. It is recognized that each of the PMOS transistors 106-110 is generally of a given size (i.e., have a particular gate width) and resistance to adequately charge the secondary voltage rail 104 (i.e., the PMOS transistors are designed and/or chosen to handle the necessary current drawn from the first power rail 102 and to transfer the voltage from the first power rail 102 to the secondary voltage rail 104. In one embodiment, each of the PMOS transistors 106-110 are identical. In other embodiments, each of the PMOS transistors 106-110 are of a similar size and have a similar resistance.
Although only three PMOS transistors 106-110 are illustrated, it is recognized that additional PMOS transistors may be added. Additionally, it is further recognized that other types of transistors (e.g., NMOS transistors) can be used with little alteration to the overall circuit design. As configured, each PMOS transistor 106-110 has its source terminal coupled to the first power rail 102 and its drain terminal coupled to the secondary voltage rail 104 while each gate terminal is coupled to receive a sleep signal 112. The state of the sleep signal 112 determines whether each of the PMOS transistors 106-110 is conducting (i.e., acting as a closed switch) or not conducting (i.e., acting as an open switch). The sleep signal 112 may be generated by any suitable device located on or off the IC. In one embodiment, a suitable state machine is used to enable or disable the sleep signal and is responsive to a determination that a specific voltage island is required to perform a given task. In the event a given voltage island is not required to work or perform a task, the state machine enables the sleep signal (i.e., it puts the voltage island to sleep). In the event a given voltage island is required to work, the state machine disables the sleep signal (i.e., it wakes up or powers up the island).
In the prior art example of FIG. 1, the gate terminals of each of the PMOS transistors 106-110 are coupled in a daisy chain configuration 114 having buffers 116-120 delaying each PMOS transistor's receipt of the sleep signal 112 by a predetermined interval of time. As recognized, the predetermined interval of time is determined by the delay created by each of the buffers 116-120. In one embodiment, each buffer 116-120 includes two logical inverter circuits (e.g., logical inverter circuits 122, 124 of buffer 116) that add an identifiable delay. Using this configuration, PMOS transistors 106-110 may be serially turned on or off. One having ordinary skill in the art will recognize that serially turning on each PMOS transistor 106-110 avoids pitfalls of similar architectures that do not delay the switching of each PMOS transistor. Such prior art systems incorporating multiple transistors without a delay are essentially equivalent to one large switch or transistor. When switched closed, the large transistor turns on strongly, thereby providing a large, instantaneous source to drain current (i.e., current draw from the first power rail 102) and noise (i.e., voltage fluctuations and IR drops) on the first power rail 102. Since the amount of current drawn from the first power rail is proportional to the size of the PMOS transistor, it is beneficial to serially turn on each PMOS transistor 106-110 at a slightly different time as determined by buffers 116-120. In this manner, the current draw is distributed over time to reduce the noise on the first power rail 102. Therefore, because PMOS transistor 106 is the first in the daisy chain configuration 114, buffer 116 is optional.
Because PMOS transistors 106-110 are used in the prior art example of FIG. 1, a sleep signal 112 representing a logical 0 acts to “close the switch” and power up the secondary voltage rail 104. Similarly, a sleep signal 112 representing a logical 1 acts to “open the switch” and disconnect the secondary voltage rail 104 from the first voltage rail 102 allowing the voltage on the secondary voltage rail 104 to float. One having ordinary skill in the art will recognize that a logical 1 ideally matches the voltage level of the first power rail (e.g., Vdd, global) and that a logical 0 ideally matches 0 V.
While the prior art system of FIG. 1 operates to power up the secondary voltage rail 104 to the voltage level of the first power rail 102, this technique still draws unnecessarily large source to drain current from the first power rail 102, which leads to noise on the first power rail 102. The large current draw may also cause possible electromigration (“EM”) violations due to the relative size of the PMOS transistors 106-110. As known in the art, EM violations result when the current levels in a physical electronic connection are increased to the point where the connection physically breaks down and possibly burns. EM violations may occur from, for example, surpassing a maximum DC current, a maximum peak AC current, a maximum RMS AC current, etc.
Another prior art system (not illustrated) incorporates the general layout of FIG. 1 without buffers 116-120 but varies the source to gate voltage of the transistors over time by altering the sleep signal 112. In effect, this solution weakly turns on the common gate of PMOS transistors 106-110 and then, after some predetermined delay, fully turns on PMOS transistors 106-110. While this helps reduce the instantaneous current draw and thus reduces the amount of noise on the first power rail 102, the implementation of a varied sleep signal and the determination of the time delay are the result of complex circuit, load and device analysis performed during IC design. Moreover, because there is no feedback from the secondary voltage rail regarding its relative charge during the power up sequence (i.e., the control is considered an open loop control), the delay and voltage variation is programmed using the assumption that the secondary voltage rail is fully discharged. Because the secondary voltage rail is not always fully discharged when a power up sequence is required, this preprogrammed (e.g., “hard”) delay and voltage variation of the sleep signal may not be the most efficient way of powering up the secondary voltage rail 104.
A third prior art solution (not illustrated) is similar to FIG. 1 and is the equivalent of turning on a small part of the plurality of switches 105 initially and then, after some predetermined delay, turning on the remainder of the plurality of switches 105. This solution may be implemented using the general configuration of FIG. 1 but by replacing, for example, the first PMOS transistor 106 with a smaller PMOS transistor having a smaller gate width. The substituted smaller PMOS transistor operates to allow only a minimal amount of current draw (due to its relative size) before the remaining PMOS transistors 108-110 are switched closed. While this third system helps reduce noise on the first power rail 102, the relative size of the smaller PMOS transistor(s) is design and implementation specific. More importantly, the delay is predetermined (i.e., “hard” and inflexible). Similar to the second system presented above, it fails to consider the relative charge on the secondary voltage rail 104 during power up and, thus, is also an open loop control system. The third system is also similar to the second system above as it requires complex circuit, load and device analysis performed during IC design to determine a suitable delay.
While the prior art illustrates how to charge a secondary voltage rail, it does so in an inefficient manner that may lead to large amounts of instantaneous current draw from the first power rail, large noise (e.g., large IR drops) on the first power rail, and possible EM violations throughout the circuit. Accordingly, a need exists to limit these effects when powering up a secondary voltage rail. A further need exists for powering up a secondary voltage rail without using open loop controlled sleep signals having voltage variations over time. A further need exists for powering up a secondary voltage rail with regard to the current charge present on the secondary voltage rail. A further need exists for powering up a secondary voltage rail without regard to the particular circuit design or implementation.